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? semiconductor component s industries, llc, 2017 1 publication order number : february 2017 - rev. 0 le25u40pcmc/d www.onsemi.com ordering information see detailed ordering and shipping info rmation on page 23 of this data sheet. * this product is licensed from s ilicon storage technology, inc. (usa). le25u40pcmc serial flash memory 4 mb (512k x 8) overview the le25u40pcmc is a spi bus flash me mory device with a 4m bit (512k ? 8-bit) configuration that adds a high performance dual output and dual i/o function. it uses a single 2.5 v power supply. while making the most of the features inherent to a serial flas h memory device, the le25u40pcmc is housed in an 8-pin ultra-miniature p ackage. all these features make this device ideally suited to storing program in applications such as portable information devices, which are required to have increasingly more compact dimensions. the le25u40pcmc also has a sm all sector erase capability which makes the device ideal for storing parameters or data that have fewer rewrite cycles and conventional eeprom s cannot handle due to insufficient capacity. features ? read/write operations enabled by single 2.5 v power supply : 2.3 to 3.6 v supply voltage range ? operating frequency : 30 mhz ? temperature range : ? 40 to +105 ? c ? serial interface : spi mode 0, mode 3 supported / dual output, dual i/o supported ? sector size : 4k bytes/sm all sector, 64k bytes/sector ? small sector erase, sector erase, chip erase functions ? page program function (256 bytes / page) ? block protect function ? highly reliable read/write number of rewrite times : 100,000 times small sector erase time : 40 ms (typ), 150 ms (max) sector erase time : 80 ms (typ), 250 ms (max) chip erase time : 250 ms (typ.), 2.0 s (max) page program time : 4.0 ms / 256 bytes (typ), 5.0 ms / 256 bytes (max) ? status functions : ready/busy information, protect information ? data retention period : 20 years ? package : sop8j (2 00 mil), case 751cu soic-8 / sop8j (200 mil)
le25u40pcmc www.onsemi.com 2 package dimensions unit : mm figure 1 pin assignments top view cs so/sio1 wp v ss v dd hold sck si/sio0 1 2 3 4 8 7 6 5 soic-8 / sop8j (200 mil) case 751cu issue o to
le25u40pcmc www.onsemi.com 3 figure 2 block diagram table 1 pin description symbol pin name description sck serial clock this pin controls the data input/output timing. the input data and addresses are latched synchronized to t he rising edge of the serial clock, and the data is output synchronized to the falling edge of the serial clock. si/sio0 serial data input / serial data input output the data and addresses are input from this pin, and latc hed internally synchronized to the rising edge of the serial clock. it changes into the output pin at dual output and it changes into the input output pin at dual i/o. so/sio1 serial data input / serial data input output the data stored inside the device is output from this pin synchronized to the falling edge of the serial clock. it changes into the output pin at dual output and it changes into the input ou tput pin at dual i/o. cs chip select the device becomes active when the logic level of this pin is low; it is deselected and placed in standby status when the logic level of the pin is high. wp write protect the status register writ e protect (srwp) takes effect when the logic level of this pin is low. hold hold serial communication is suspended when the logic level of this pin is low. v dd power supply this pin supplies th e 2.3 to 3.6 v supply voltage. v ss ground this pin supplies the 0 v supply voltage. 4m bit flash eeprom cell array y-decoder i/o buffers & data latches cs sck si/sio0 hold wp so/sio1 x- decoder address buffers & latches serial interface control logic
le25u40pcmc www.onsemi.com 4 device operation the read, erase, program and other required functions of the device are executed through the command registers. the serial i/o corrugate is shown in figure 3 and the command list is shown in table 2. at the falling cs edge the device is selected, and serial input is enabled for the comma nds, addresses, etc. these i nputs are normalized in 8 bit units and taken into the device interior in synchronization with the rising edge of sck, which causes the device to execute operation according to the command that is input. the le25u40pcmc supports both serial interface spi mode 0 and spi mode 3. at the falling cs edge, spi mode 0 is automatically selected if the logic level of sck is low, and spi mode 3 is automatically selected if the logic level of sck is high. figure 3 i/o waveforms table 2 command settings command 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle nth bus cycle read 03h a23-a16 a15-a8 a7-a0 rd *1 rd *1 rd *1 high speed read 0bh a23-a16 a15-a8 a7-a0 x rd *1 rd *1 dual read 3bh a23-a16 a15-a8 a7-a0 z rd *1 rd *1 dual i/o read bbh a23-a8 a7-a0,x, z rd *1 rd *1 rd *1 rd *1 small sector erase 20h / d7h a23-a16 a15-a8 a7-a0 sector erase d8h a23-a16 a15-a8 a7-a0 chip erase 60h / c7h page program 02h a23-a16 a15-a8 a7-a0 pd *2 pd *2 pd *2 write enable 06h write disable 04h power down b9h status register read 05h status register write 01h data jedec id read 9fh id read abh x x x power down b9h exit power down mode abh explanatory notes for table 2 "x" signifies "don't care" (that is to say, any valu e may be input)., "z? signifies " high impedance ". the "h" following each code indicates that the number given is in hexadecimal notation. addresses a23 to a19 for a ll commands are "don't care". *1: "rd" stands for read data. *2: "pd" stands for page program data. cs sck so si high impedance data data 1st bus 2nd bus 8clk mode0 mode3 nth bus msb (bit7) lsb (bit0)
le25u40pcmc www.onsemi.com 5 table 3 command settings 4m bit sector(64kb) small sector address space(a23 to a0) 7 127 07f000h 07ffffh to 112 070000h 070fffh 6 111 06f000h 06ffffh to 96 060000h 060fffh 5 95 05f000h 05ffffh to 80 050000h 050fffh 4 79 04f000h 04ffffh to 64 040000h 040fffh 3 63 03f000h 03ffffh to 48 030000h 030fffh 2 47 02f000h 02ffffh to 32 020000h 020fffh 1 31 01f000h 01ffffh to 16 010000h 010fffh 0 15 00f000h 00ffffh to 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh
le25u40pcmc www.onsemi.com 6 description of commands and their operations a detailed description of the functions and operations corresponding to each command is presented below. 1. standard spi read there are two read commands, the standard spi read command and high-speed read command. 1-1. read command consisting of the first through fourth bus cycles, the 4 bus cycle read command in puts the 24-bit addresses following (03h). the data is output from so on the falling clock edge of fourth bus cycle bit 0 as a reference. "figure 4-a read" shows the timing waveforms. figure 4-a read 1-2. high-speed read command consisting of the first through fifth bus cycles, the high-speed read command inputs the 24-bit addresses and 8 dummy bits following (0bh). the data is output from so using the falling clock edge of fifth bus cycle bit 0 as a reference. "figure 4-b high-speed read" shows the timing waveforms. figure 4-b high-speed read n+2 n+1 n cs high impedance data data data sck so si 03h a dd. a dd. a dd. 15 msb msb msb 0 1 2 3 4 5 6 7 8 23 16 24 31 39 47 8clk mode0 mode3 32 40 n+2 n+1 n cs high impedance data data data sck so si 0bh a dd. a dd. a dd. x 15 msb msb msb 0 1 2 3 4 5 6 7 8 23 16 24 31 32 39 40 47 48 55 mode3 mode0 8clk msb
le25u40pcmc www.onsemi.com 7 2. dual read there are two dual read commands, the dual read comm and and the dual i/o read command. they achieve the twice speed-up from a high-speed read command. 2-1. dual read command the dual read command changes si/sio0 into the output pin function in addition to so/sio1, makes the data output ? 2 bit and has achieved a high-speed output. consisting of the first through fifth bus cycles, the dual read command inputs the 24-bit addresses and 8 dummy bits fo llowing (3bh). data1 (bit7, bit5, bit3 and bit1) is output from si/sio0 and data0 (bit6, bit4, bit2 and bit0) is output from so/sio1 on the falling clock edge of fifth bus cycle bit 0 as a reference. "figur e 5-a dual read" shows the timing waveforms. figure 5-a dual read 2-2. dual i/o read command the dual i/o read command changes si/s io0 and so/sio1 into the input output pin function, makes the data input and output ? 2 bit and has achieved a high-speed output. consisting of the first through third bus cycles, the dual i/o read command inputs the 24-bit addresses and 4 dummy clocks following (bbh). the format of the address input and the dummy bit input is the ? 2 bit input. add1 (a23, a21, -, a3 and a1) is input from s0/sio1 and add0 (a22, a20, -, a2 and a0) is input from si/sio0. 2clk of th e latter half of the dummy clock is in the state of high impedance, the controller can switch i/o for this period. data1 (bit7, bit5, bit3 and bit1) is output from si/sio0 and data0 (bit6, bit4, bit2 and bit0) is output from so/sio1 on the falling clock edge of third bus cycle bit 0 as a reference. "figure 5-b dual i/o read" shows the timing waveforms. figure 5-b dual i/o read when sck is input continuously after the read command has been input and the data in the designated addresses has been output, the address is automatically incremented inside the device while sck is being input, and the corresponding data is output in sequence. if the sck inpu t is continued after the internal address arrives at the highest address (7ffffh), the internal address returns to th e lowest address (00000h), and data output is continued. by setting the logic level of cs to high, the device is deselected, and the read cycle ends. while the device is deselected, the output pin so is in a high-impedance state. cs high impedance data1 data1 data1 sck so/sio1 si/sio0 3bh a dd. a dd. a dd. 15 msb msb 0 1 2 3 4 5 6 7 8 23 16 24 31 32 39 40 43 44 47 mode3 mode0 8cl msb msb n+2 n+1 n data0 data0 data0 4cl 4cl data0 b6,b4,b2,b0 data1 b7,b5,b3,b1 dummy bit cs high impedance data1 data1 data1 sck so/sio1 si/sio0 bbh x a dd1:a22,a20-a2,a0 msb msb 0 1 2 3 4 5 6 7 8 19 22 23 24 27 28 31 mode3 mode0 8cl msb msb n+2 n+1 n data0 data0 data0 4clk data0 b6,b4,b2,b0 data1 b7,b5,b3,b1 dummy bit 20 21 a dd2:a23,a21-a3,a1 x 2clk 2clk 12clk
le25u40pcmc www.onsemi.com 8 3. status registers the status registers hold the operating and setting statuses inside the device, and this information can be read (status register read) and the protect information can be rewritten (sta tus register write). there are 8 bits in total, and "table 4 status registers" gives the significance of each bit. table 4 status registers bit name logic function power-on time information bit0 rdy 0 ready 0 1 erase/program bit1 wen 0 write disabled 0 1 write enabled bit2 bp0 0 block protect information protecting area switch nonvolatile information 1 bit3 bp1 0 nonvolatile information 1 bit4 bp2 0 nonvolatile information 1 bit5 tb 0 block protect upper side/lower side switch nonvolatile information 1 bit6 reserved bits 0 bit7 srwp 0 status register write enabled nonvolatile information 1 status register write disabled 3-1. status register read the contents of the status registers can be read using the status register read command. this command can be executed even during th e following operations. ? small sector erase, sector erase, chip erase ? page program ? status register write "figure 6 status register read" shows the timing waveforms of status register read. consisting only of the first bus cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the clock (sck) with which the eighth bit of (05h) has been input. in terms of the output sequence, srwp (bit 7) is the first to be output, and each time one cloc k is input, all the other bits up to rdy (bit 0) are output in sequence, synchronized to the falling clock edge. if the clock input is continued after rdy (bit 0) has been output, the data is output by returning to the bit (srwp) that was first output, after which the output is repeated for as long as the clock input is continued. the data can be read by the status register read command at any time (even during a program or erase cycle). figure 6 status register read cs sck si so msb msb msb 05h data data high impedance 8 3 2 1 0 7 6 5 4 15 23 mode 3 mode 0 8clk 16 data msb
le25u40pcmc www.onsemi.com 9 3-2. status register write the information in status registers bp0, bp1, bp2, tb and srwp can be rewritten using the status register write command. rdy , wen and bit 6 are read-only bits and cannot be re written. the information in bits bp0, bp1, bp2, tb and srwp is stored in the non-volatile memory, and when it is written in these bits, the contents are retained even at power-down. "figure 6 status register write" shows the timing waveforms of status register write, and figure 20 shows a status register write flowchart. consisti ng of the first and second bus cycles, the status register write command initiates the internal write operation at the rising cs edge after the data has been input following (01h). erase and program are performed au tomatically inside the device by status register write so that erasing or other processing is unnecessary before executing the command. by the operation of this command, the information in bits bp0, bp1, bp2, tb and sr wp can be rewritten. since bits rdy (bit 0), wen (bit 1) and bit 6 of the status register cannot be written, no problem will arise if an a ttempt is made to set them to any value when rewriting the status register. status register write ends can be detected by rdy of status register read. to initiate status register write, the logic level of the wp pin must be set high and status register wen must be set to "1". figure 6 status register write 3-3. contents of each status register rdy (bit 0) the rdy register is for detecting the write (program, erase and status register write) end. when it is "1", the device is in a busy state, and when it is "0", it means that write is completed. wen (bit 1) the wen register is for detecting whether the device can perform write operations. if it is set to "0", the device will not perform the write operation even if the write command is i nput. if it is set to "1", the device can perform write operations in any area that is not block-protected. wen can be controlled using the write enable and write disable commands. by inputting the write enable command (06h), wen can be set to "1"; by inputting the write disa ble command (04h), it can be set to "0." in the following states, wen is automatically set to "0" in order to protect against unintentional writing. ? at power-on ? upon completion of small sector er ase, sector erase or chip erase ? upon completion of page program ? upon completion of status register write * if a write operation has not been performed inside th e le25u40pcmc because, for in stance, the command input for any of the write operations (small sector er ase, sector erase, chip erase, page program, or status register write) has failed or a write operation has been performed for a protec ted address, wen will retain the status established prior to the issue of the command concerned. furthermore, its state will not be changed by a read operation. t srw self-timed write cycle sck si high impedance so cs data 01h 15 0 1 2 3 4 5 6 7 8 mode3 mode0 8clk wp t wph t wps msb
le25u40pcmc www.onsemi.com 10 bp0, bp1, bp2, tb (bits 2, 3, 4, 5) block protect bp0, bp1, bp2 and tb ar e status register bits that can be rewritten, and the memory space to be protected can be set depending on these bits. for the setting conditions, refer to "table 5 protect level setting conditions". bp0, bp1, and bp2 are used to select the protected area and tb to allocate the protected area to the higher-order address area or lower-order address area. table 5 protect level setting conditions protect level status register bits protected area tb bp2 bp1 bp0 0 (whole area unprotected) x 0 0 0 none t1 (upper side 1/8 protected) 0 0 0 1 07ffffh to 070000h t2 (upper side 1/4 protected) 0 0 1 0 07ffffh to 060000h t3 (upper side 1/2 protected) 0 0 1 1 07ffffh to 040000h b1 (lower side 1/8 protected) 1 1 0 1 00ffffh to 000000h b2 (lower side 1/4 protected) 1 1 1 0 01ffffh to 000000h b3 (lower side 1/2 protected) 1 1 1 1 03ffffh to 000000h 4 (whole area protected) x 1 x x 07ffffh to 000000h * chip erase is enabled only when the protect level is 0. srwp (bit 7) status register write protect srwp is the bit for protecting the status registers, and its information can be rewritten. when srwp is "1" and the logic level of the wp pin is low, the status register write command is ignored, and status registers bp0, bp1, bp2, tb and srwp ar e protected. when the logic level of the wp pin is high, the status registers are not protected regardless of the srwp state. the srwp setting conditions are shown in "table 6 srwp setting conditions". table 6 srwp setting conditions wp pin srwp status register protect state 0 0 unprotected 1 protected 1 0 unprotected 1 unprotected bit 6 are reserved bits, and have no significance.
le25u40pcmc www.onsemi.com 11 4. write enable before performing any of the operations listed below, the device must be pl aced in the write enable state. operation is the same as for setting status register wen to "1", and the state is enabled by inputting the write enable command. "figure 8 write enable" shows the timing waveforms when the write enable operation is performed. the write enable command consists only of the first bus cycle, and it is initiated by inputting (06h). ? small sector erase, sector erase, chip erase ? page program ? status register write 5. write disable the write disable command sets status register wen to "0" to prohibit unintentional writing. "figure 9 write disable" shows the timing waveforms. the write disable command consists only of the first bus cycle, and it is initiated by inputting (04h). the write disable state (wen "0") is exited by setting wen to "1" using the write enable command (06h). figure 8 write enable figure 9 write disable 6. power-down the power-down command sets all the commands, with the exception of the silicon id read command and the command to exit from power-down, to the acceptance prohibited state (p ower-down). "figur e 10 power-down" shows the timing waveforms. the power- down command consists only of the fi rst bus cycle, and it is initiated by inputting (b9h). however, a power-down command issued duri ng an internal write operation will be ignored. the power-down state is exited using the power-down exit comm and (power-down is exited also when one bus cycle or more of the silicon id read command (abh) has been input). "figure 11 exiting from power-down" shows the timing waveforms of the power-down exit command. figure 10 power-down figure 11 exiting from power-down sck si high impedance so cs 06h 0 1 2 3 4 5 6 7 mode3 mode0 8clk sck si high impedance so cs 04h 0 1 2 3 4 5 6 7 mode3 mode0 8clk msb msb sck si high impedance so cs b9h 0 1 2 3 4 5 6 7 mode3 mode0 8clk sck si high impedance so cs a bh 0 1 2 3 4 5 6 7 mode3 mode0 8clk t pdr t dp power down mode power down mode msb msb
le25u40pcmc www.onsemi.com 12 7. small sector erase small sector erase is an operation that sets the memory cell da ta in any small sector to "1". a small sector consists of 4kbytes. "figure 12 small sector erase" shows the timing waveforms, and figure 21 shows a small sector erase flowchart. the small sector erase comm and consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (20h) or (d7h). addresses a18 to a12 are valid, and addresses a23 to a19 are "don't care". after the command has been input, the internal erase operation starts from the rising cs edge, and it ends automatically by the control exercised by the internal ti mer. erase end can also be det ected using status register rdy . figure 12 small sector erase 8. sector erase sector erase is an operation that sets the memory cell data in any sector to "1". a sector consists of 64k bytes. "figure 13 sector erase" shows the timing waveforms, an d figure 21 shows a sector erase flowchart. the sector erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (d8h). addresses a18 to a16 are valid, and ad dresses a23 to a19 are "don 't care". after the command has been input, the internal erase operation starts from the rising cs edge, and it ends automatically by the control exercised by the internal timer. erase end can also be detected using status register rdy . figure 13 sector erase self-timed erase cycle sck si high impedance so cs t sse add. 20h / d7h add. add. 15 0 1 2 3 4 5 6 7 8 23 16 24 31 mode3 mode0 8clk msb sck si high impedance so cs t se self-timed erase cycle add. d8h add. add. 15 0 1 2 3 4 5 6 7 8 23 16 24 31 mode3 mode0 8clk msb
le25u40pcmc www.onsemi.com 13 9. chip erase chip erase is an operation that sets the memory cell data in all the sectors to "1". "fig ure 14 chip erase" shows the timing waveforms, and figure 21 shows a chip erase flowchar t. the chip erase command consists only of the first bus cycle, and it is initiated by inputting (60h) or (c 7h). after the command has been input, the internal erase operation starts from the rising cs edge, and it ends automatically by the control exercised by the internal timer. erase end can also be detected using status register rdy . figure 14 chip erase 10. page program page program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page (page addresses: a18 to a8). before initiating page progr am, the data on the page concerned must be erased using small sector erase, sector erase, or chip erase. "figur e 15 page program" shows the page program timing waveforms, and figure 22 shows a page program flowchart. after the falling cs , edge, the command (02h) is input followed by the 24-bit addresses. addresses a18 to a0 are valid. the program data is then loaded at each rising clock edge until the rising cs edge, and data loading is continued until the rising cs edge. if the data loaded has exceeded 256 bytes, the 256 bytes loaded last are programm ed. the program data must be loaded in 1-byte increments, and the program operation is not performed at the rising cs edge occurring at any other timing. figure 15 page program sck si high impedance so cs t che self-timed erase cycle 60h / c7h 0 1 2 3 4 5 6 7 mode3 mode0 8clk msb t pp self-timed program cycle sck si high impedance so cs pd a dd. a dd. 02h a dd. pd 15 0 1 2 3 4 5 6 7 8 23 16 24 31 32 39 40 47 mode3 mode0 8clk pd 2079 msb
le25u40pcmc www.onsemi.com 14 11. silicon id read id read is an operation that reads the manufacturer code and device id information. the silicon id read command is not accepted during writing. there are two methods of readin g the silicon id, each of which is assigned a device id. in the first method, the read command sequence consists only of the first bus cycle in which (9fh) is input. in the subsequent bus cycles, the manufacturer code 62h which is assigned by jedec, 2-byte device id code (memory type, memory capacity), and reserved code are output sequentia lly. the 4-byte code is output repeatedly as long as clock inputs are present, "table 7-1 jedec id code " lists the silicon id codes and "figure 16-a jedec id read" shows the jedec id read timing waveforms. the second method involves inputting the id read command. this command consists of the first through fourth bus cycles, and the one bite silicon id can be read when 24 dummy bits are input after (abh). "table 7-2 id code " lists the silicon id codes and "figure 16-b id r ead" shows the id read timing waveforms. if the sck input persists after a device code is read, that device code continues to be output. the data output is transmitted starting at the falling edge of the clock for b it 0 in the fourth bus cycle and the silicon id read sequence is finished by setting cs high. table 7-1 jedec id code table 7-2 id code output code output code manufacturer code 62h 1 byte device id 6e (le25u40pcmc) 2 byte device id memory type 06h memory capacity code 13h(4m bit) device code 1 00h figure 16-a jedec id read figure 16-b id read cs high impedance 13h 06h 62h sck so si 9fh 15 msb msb msb 0 1 2 3 4 5 6 7 8 23 16 24 31 39 8cl mode0 mode3 32 00h msb 62h msb cs high impedance 6eh 6eh sck so si a bh x x 15 msb msb 0 1 2 3 4 5 6 7 8 23 16 24 31 39 8cl mode0 mode3 32 x
le25u40pcmc www.onsemi.com 15 12. hold function using the hold pin, the hold function suspends serial communication (it places it in the hold status). "figure17 hold " shows the timing waveforms. the device is placed in the hold stat us at the falling hold edge while the logic level of sck is low, and it exits from the hold status at the rising hold edge. when the logic level of sck is high, hold must not rise or fall. the hold function takes effect when the logic level of cs is low, the hold status is exited and serial communication is reset at the rising cs edge. in the hold status, the so output is in the high- impedance state, and si and sck are "don't care". figure 17 hold 13. power-on in order to protect against unintentional writing, cs must be within at v dd ? 0.3 to v dd + 0.3 on power-on. after power-on, the supply voltage has stabilized at v dd min. or higher, waits for t pu before inputting the command to start a device operation. the device is in the standby state and not in the powe r-down state after pow er is turned on. to put the device into the power-down state, it is necessary to enter a power-down command. figure 18 power-on timing cs hold sck so a ctive hold a ctive t hh t hs t hlz t hhz high impedance t hh t hs v dd (max) v dd (min) v dd 0v t pu cs = v dd level full access allowed
le25u40pcmc www.onsemi.com 16 14. hardware data protection le25u40pcmc incorporates a power-on reset function. the following conditions must be met in order to ensure that the power reset circuit will operate stably. no guarantees are given for data in the event of an instantaneous power failure occurring during the writing period. figure 19 power-down timing power-on timing parameter symbol spec unit min max power-on to operation time t pu 100 s power-down time t pd 10 ms power-down voltage t bot 0.2 v 15. software data protection the le25u40pcmc eliminates the possibility of unintentional operations by not recognizing commands under the following conditions. ? when a write command is input and the rising cs edge timing is not in a bus cycle (8 clk units of sck) ? when the page program data is not in 1-byte increments ? when the status register write command is input for 2 bus cycles or more 16. decoupling capacitor a 0.1 ? f ceramic capacitor must be provided to each device and connected between v dd and v ss in order to ensure that the device will operate stably. v dd (max) v dd (min) v dd 0v vbot t pd
le25u40pcmc www.onsemi.com 17 specifications absolute maximum ratings parameter symbol conditions ratings unit maximum supply voltage v dd max with respect to v ss ? 0.5 to +4.6 v dc voltage (all pins) vin/vout with respect to v ss ? 0.5 to v dd +0.5 v storage temperature tstg ? 55 to +150 ? c operating conditions parameter symbol conditions ratings unit operating supply voltage v dd 2.3 to 3.6 v operating ambient temperature topr ? 40 to +105 ? c allowable dc operating conditions parameter symbol conditions ratings unit min typ max read mode operating current i ccr sck = 0.1v dd / 0.9v dd , hold = wp = 0.9v dd , output = open single 25 mhz 6 ma 30 mhz 10 dual 30 mhz 12 ma write mode operating current (erase + page program) i ccw t sse = t se = t che = typ., t pp = max 15 ma cmos standby current i sb cs = v dd , hold = wp = v dd , si = v ss / v dd , so = open 50 ? a power-down standby current i dsb cs = v dd , hold = wp = v dd , si = v ss / v dd , so = open 50 ? a input leakage current i li 2 ? a output leakage current i lo 2 ? a input low voltage v il ? 0.3 0.3v dd v input high voltage v ih 0.7v dd v dd +0.3 v output low voltage v ol i ol = 100 ? a, v dd = v dd min 0.2 v i ol = 1.6 ma, v dd = v dd min 0.4 output high voltage v oh i oh = ? 100 ? a, v dd = v dd min v dd ? 0.2 v data hold, rewriting frequency parameter condition min max unit rewriting frequency program / erase 100,000 times/ sector status resister write 1,000 times data hold 20 year pin capacitance at ta=25 ? c, f=1mhz parameter symbol conditions ratings unit max output pin capacitance c so v so = 0 v 12 pf input pin capacitance c in v in = 0 v 6 pf note : these parameter values do not represent the results of measurements undertaken for all devices but rather values for som e of the sampled devices. stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility.
le25u40pcmc www.onsemi.com 18 ac characteristics parameter symbol ratings unit min typ max clock frequency read instruction (03h) f clk 0.01 25 mhz all instructions except for read (03h) 0.01 30 mhz input signal rising/falling time t rf 0.1 v/ns sck logic high level pulse width t clhi 16 ns sck logic low level pulse width t cllo 16 ns cs setup time t css 10 ns cs hold time t csh 10 ns data setup time t ds 5 ns data hold time t dh 5 ns cs wait pulse width t cph 25 ns output high impedance time from cs t chz 15 ns output data time from sck t v 10 14 ns output data hold time t ho 1 ns output low impedance time from sck t clz 0 ns hold setup time t hs 7 ns hold hold time t hh 3 ns output low impedance time from hold t hlz 9 ns output high impedance time from hold t hhz 9 ns wp setup time t wps 20 ns wp hold time t wph 20 ns power-down time t dp 3 ? s power-down recovery time t pdr 3 ? s write status register time t srw 5 15 ms page programming cycle time t pp 4 5 ms small sector erase cycle time t sse 40 150 ms sector erase cycle time t se 80 250 ms chip erase cycle time t che 0.25 2.0 s ac test condtions input pulse level 0.2v dd to 0.8v dd input rising/falling time 5 ns input timing level 0.3v dd , 0.7v dd output timing level 1/2 ? v dd output load 30 pf note : as the test conditions for "typ", the measurements are conducted using 2.5 v for v dd at room temperature. 0.8v dd 0.2v dd 0.7v dd 1/2v dd 0.3v dd input level input / output timing level product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
le25u40pcmc www.onsemi.com 19 timing waveforms serial input timing serial output timing hold timing status resistor write timing high impedance t dh t cph t ds t csh t css cs data valid so si sck high impedance t css t csh t clhi t cllo t ho t chz t clz si t v cs so sck data valid si cs sck hold t hh t hs t hh t hs t hhz t hlz high impedance t wph t wps cs wp
le25u40pcmc www.onsemi.com 20 figure 20 status register write flowchart status register write start 05h set status register read command set status register write command status register write start on rising edge of cs end of status register write yes bit 0= ?0? ? 06h write enable 01h no * automatically placed in write disabled state at the end of the status register write data
le25u40pcmc www.onsemi.com 21 figure 21 erase flowcharts start 05h set status register read command set small sector erase command address 1 address 2 start erase on rising edge of cs end of erase bit 0 = ?0? ? yes small sector erase address 3 06h write enable 20h / d7h no * automatically placed in write disabled state at the end of the erase start 05h set status register read command set sector erase command address 1 address 2 start erase on rising edge of cs end of erase bit 0 = ?0? ? yes sector erase address 3 06h write enable d8h no * automatically placed in write disabled state at the end of the erase
le25u40pcmc www.onsemi.com 22 figure 22 page program flowchart start 05h set status register read command set chip erase command start erase on rising edge of cs end of erase bit 0 = ?0? ? yes chip erase 06h write enable 60h / c7h no * automatically placed in write disabled state at the end of the erase page program start 05h set status register read command set page program command address 1 address 2 start program on rising edge of cs end of programming yes bit 0= ?0? ? address 3 06h write enable 02h no * automatically placed in write disabled state at the end of the programming operation. data 0 data n
le25u40pcmc www.onsemi.com 23 on semiconductor and the on semiconductor logo are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries in the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and othe r intellectual property. a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does on semiconductor assume any liability arising out of the app lication or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, regulations and safety require ments or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the rights of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life sup port systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended fo r implantation in the human body. should buyer purchase or use on semiconductor products for any such unintended or unauthorized application, buyer sh all indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, d amages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resal e in any manner. figure 23 marking information ordering information device package shipping (qty / packing) LE25U40PCMC-AH-1 soic-8 / sop8j (200 mil) (pb-free / halogen free) 2000 / tape & reel ? for information on tape and reel specifications, including part orientation and tape sizes, plea se refer to our tape and reel packaging specifications brochure, brd8011/d. h ttp://www.onsemi.com/pub_lin k/collateral/brd8011-d.pdf 25u40pc alyw sop8j (le25u40pcmc) 25u40pc = specific device code a = assembly location l = wafer lot traceability yw = two digits year and work week date coding

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